1. Field of the Invention
The present invention generally relates to a method for fabricating semiconductor devices, and more particularly, relates to a photoresist shrink process and an organic material layer having low dielectric constant. The present invention is capable of making gate structures having small dimensions, and in providing semiconductor devices with low production cost.
2. Description of the Prior Art
Recently, demand for semiconductor devices has rapidly increased owing to widespread use of the integrated electronic circuit. In particular, as more than hundreds or thousands of electrical components are integrated into the ICs, means for scaling down the dimension of the MOSFET and for reducing fabrication costs has become imperative.
In logic product applications, the smaller the gate structure the faster the handling speed and the higher the integrity of semiconductor devices. Therefore, the production of gate structures having small dimension will be the most important trend in the present day. For the conventional semiconductor devices, when the optical resolution is required to achieve gate structures with small dimension, the size of gate electrodes need to be smaller and smaller, also the thinner the more exposed, and the photoresist layer needs to be thin comparatively. This thin photoresist layer might not be thick enough for blocking the etching process in the follow-up fabrication, hence, is not able to be used in the etching process.
Consequently, semiconductor devices with small dimensions and low production cost are desired urgently.